package CommSub

import chisel3._
import chisel3.util._

class AXIClockConverterBlackBox extends BlackBox{
    val io = IO(new Bundle{
        val s_axi_awaddr    = Input(UInt(64.W))
        val s_axi_awlen     = Input(UInt(8.W))
        val s_axi_awsize    = Input(UInt(3.W))
        val s_axi_awburst   = Input(UInt(2.W))
        val s_axi_awlock    = Input(UInt(1.W))
        val s_axi_awcache   = Input(UInt(4.W))
        val s_axi_awprot    = Input(UInt(3.W))
        val s_axi_awregion  = Input(UInt(4.W))
        val s_axi_awqos     = Input(UInt(4.W))
        val s_axi_awvalid   = Input(UInt(1.W))
        val s_axi_awready   = Output(UInt(1.W))
        val s_axi_wdata     = Input(UInt(512.W))
        val s_axi_wstrb     = Input(UInt(64.W))
        val s_axi_wlast     = Input(UInt(1.W))
        val s_axi_wvalid    = Input(UInt(1.W))
        val s_axi_wready    = Output(UInt(1.W))
        val s_axi_bresp     = Output(UInt(2.W))
        val s_axi_bvalid    = Output(UInt(1.W))
        val s_axi_bready    = Input(UInt(1.W))
        val s_axi_araddr    = Input(UInt(64.W))
        val s_axi_arlen     = Input(UInt(8.W))
        val s_axi_arsize    = Input(UInt(3.W))
        val s_axi_arburst   = Input(UInt(2.W))
        val s_axi_arlock    = Input(UInt(1.W))
        val s_axi_arcache   = Input(UInt(4.W))
        val s_axi_arprot    = Input(UInt(3.W))
        val s_axi_arregion  = Input(UInt(4.W))
        val s_axi_arqos     = Input(UInt(4.W))
        val s_axi_arvalid   = Input(UInt(1.W))
        val s_axi_arready   = Output(UInt(1.W))
        val s_axi_rdata     = Output(UInt(512.W))
        val s_axi_rresp     = Output(UInt(2.W))
        val s_axi_rlast     = Output(UInt(1.W))
        val s_axi_rvalid    = Output(UInt(1.W))
        val s_axi_rready    = Input(UInt(1.W))
        
        val s_axi_aclk      = Input(Clock())
        val s_axi_aresetn   = Input(Bool())

        val m_axi_aclk      = Input(Clock())
        val m_axi_aresetn   = Input(Bool())

        val m_axi_awaddr    = Output(UInt(64.W))
        val m_axi_awlen     = Output(UInt(8.W))
        val m_axi_awsize    = Output(UInt(3.W))
        val m_axi_awburst   = Output(UInt(2.W))
        val m_axi_awlock    = Output(UInt(1.W))
        val m_axi_awcache   = Output(UInt(4.W))
        val m_axi_awprot    = Output(UInt(3.W))
        val m_axi_awregion  = Output(UInt(4.W))
        val m_axi_awqos     = Output(UInt(4.W))
        val m_axi_awvalid   = Output(UInt(1.W))
        val m_axi_awready   = Input(UInt(1.W))
        val m_axi_wdata     = Output(UInt(512.W))
        val m_axi_wstrb     = Output(UInt(64.W))
        val m_axi_wlast     = Output(UInt(1.W))
        val m_axi_wvalid    = Output(UInt(1.W))
        val m_axi_wready    = Input(UInt(1.W))
        val m_axi_bresp     = Input(UInt(2.W))
        val m_axi_bvalid    = Input(UInt(1.W))
        val m_axi_bready    = Output(UInt(1.W))
        val m_axi_araddr    = Output(UInt(64.W))
        val m_axi_arlen     = Output(UInt(8.W))
        val m_axi_arsize    = Output(UInt(3.W))
        val m_axi_arburst   = Output(UInt(2.W))
        val m_axi_arlock    = Output(UInt(1.W))
        val m_axi_arcache   = Output(UInt(4.W))
        val m_axi_arprot    = Output(UInt(3.W))
        val m_axi_arregion  = Output(UInt(4.W))
        val m_axi_arqos     = Output(UInt(4.W))
        val m_axi_arvalid   = Output(UInt(1.W))
        val m_axi_arready   = Input(UInt(1.W))
        val m_axi_rdata     = Input(UInt(512.W))
        val m_axi_rresp     = Input(UInt(2.W))
        val m_axi_rlast     = Input(UInt(1.W))
        val m_axi_rvalid    = Input(UInt(1.W))
        val m_axi_rready    = Output(UInt(1.W))
    })
}